The need for larger storage capacity devices, faster operating devices and/or lower power consuming devices continually drive further scaling of memory devices. However, the scaling of memory devices is constrained by design rules that are technology specific. The design rules specify the minimum feature sizes, spacings and overlaps for the component devices and interconnects, and the maximum misalignment that can occur between two masks. In addition, line width expansion and shrinkage throughout fabrication also strongly affect the design rules.
Referring to FIG. 1, an integrated circuit (IC) memory device, according to the conventional art, is shown. The IC includes a core area 110 that includes the memory cell array of the device. The IC also includes a peripheral area that may include one or more circuits such as write buffer, read buffer, data latch, address latch, address decoder and control logic. The core area is characterized by a very high circuit density and therefore the structures are fabricated with minimum feature sizes. The peripheral area may have circuits with lower densities and therefore may or may not be fabricated with minimum feature sizes. However, it is desirable to fabricate the structures in the core area using as many of the same fabrication processes as possible.
Referring now to FIGS. 2A and 2B, a top and side view representation of an exemplary portion of a peripheral structure, according to the conventional art, is shown. The exemplary peripheral structure includes a plurality of transistor structures 210 and interconnecting structures 215-225. The interconnect structures in the peripheral area may include a contact 215 coupled to the transistor 210, a via 220 coupled to the contact 215, and a plurality of lines 225 (e.g., word, bit, address, data, control or the like), wherein one of the lines 225 is coupled to the via 220.
In order to continue to scale memory devices, such as NAND flash memories, there is a continuing need to further scale the interconnects. Preferably, the interconnects should be fabricated using as few masks as possible. The resistance of interconnects should also preferably be lower than conventional interconnects. Furthermore, differences between the structures in the peripheral area and the structures in the core area should not deleteriously impact the scaling of the structures.